| US 7,533,309 B2 | ||
| Testing memories using algorithm selection | ||
| Nilanjan Mukherjee, 29290 SW. Parkway Ct., Apt 91, Wilsonville, Oreg. 97070 (US); Joseph C. Rayhawk, 15248 NW. Germantown Rd., Portland, Oreg. 97231 (US); and Amrendra Kumar, 26170 SW. Canyon Creek Rd., Apt. #203, Wilsonville, Oreg. 97070 (US) | ||
| Filed on Jun. 04, 2004, as Appl. No. 10/861,851. | ||
| Claims priority of provisional application 60/548656, filed on Feb. 26, 2004. | ||
| Prior Publication US 2005/0204231 A1, Sep. 15, 2005 | ||
| Int. Cl. G11C 29/00 (2006.01); G11C 7/00 (2006.01) | ||
| U.S. Cl. 714—718 [365/201] | 51 Claims |
| 1. A method of performing a built-in-self-test (BIST) of at least one memory element of a circuit, the method comprising:
running a first testing algorithm on the at least one memory element;
determining whether to run a second testing algorithm, the act of determining being performed during a delay following the
running of the first testing algorithm and comprising evaluating a value associated with the second testing algorithm, wherein
the value associated with the second testing algorithm is a value stored in a shift register so as to be associated with the
second testing algorithm;
running the second testing algorithm on the at least one memory element if a determination is made during the determining
act that the second testing algorithm is to be run; and
if a determination is made during the determining act that the second testing algorithm is not to be run, determining whether
to run a third testing algorithm, the act of determining comprising evaluating a value associated with the third testing algorithm,
wherein the values associated with the second and third testing algorithms are stored in different memory locations.
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