| US 7,533,300 B2 | ||
| Configurable error handling apparatus and methods to operate the same | ||
| Suresh Marisetty, Fremont, Calif. (US); Baskaran Ganesan, Bangalore (India); Gautam Bhagwandas Doshi, Bangalore (India); Murugasamy Nachimuthu, Hillsboro, Oreg. (US); Koichi Yamada, Los Gatos, Calif. (US); Jose A. Vargas, Rescue, Calif. (US); Jim Crossland, Banks, Oreg. (US); and Stan J. Domen, Roseville, Calif. (US) | ||
| Assigned to Intel Corporation, Santa Clara, Calif. (US) | ||
| Filed on Feb. 13, 2006, as Appl. No. 11/352,961. | ||
| Prior Publication US 2007/0220332 A1, Sep. 20, 2007 | ||
| Int. Cl. G06F 11/00 (2006.01) | ||
| U.S. Cl. 714—27 [714/48] | 23 Claims |
| 1. A method comprising:
determining an error handling mode from an error handling mode configuration setting for a semiconductor device;
configuring a hardware function block in the semiconductor device based on the error handling mode; and
configuring an error-handling circuit in the semiconductor device, wherein the error-handling circuit is configurable to route
error information from the hardware function block to firmware and an operating system executing on a processor core located
in the semiconductor device.
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