| US 7,533,282 B2 | ||
| Logic circuit apparatus for selectively assigning a plurality of circuit data to a plurality of programmable logic circuits for minimizing total power while maintaining necessary processing performance | ||
| Taku Ohneda, Kanagawa-ken (Japan); Shinichi Kanno, Kanagawa-ken (Japan); Masaya Tarui, Kanagawa-ken (Japan); Yukimasa Miyamoto, Kanagawa-ken (Japan); and Riku Ogawa, Tokyo (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Dec. 03, 2007, as Appl. No. 11/949,072. | ||
| Application 11/949072 is a division of application No. 11/128187, filed on May 13, 2005, granted, now 7,386,741. | ||
| Claims priority of application No. 2004-146554 (JP), filed on May 17, 2004. | ||
| Prior Publication US 2008/0100338 A1, May 01, 2008 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. G06F 1/00 (2006.01); G06F 1/32 (2006.01) | ||
| U.S. Cl. 713—320 [713/300; 326/37; 326/38] | 2 Claims |
| 1. A logic circuit apparatus, comprising:
a plurality of programmable logic circuits each configured to have a changeable circuit component based on circuit data, each
programmable logic circuit having a different processing performance;
a circuit data memory to store a plurality of circuit data and performance requirements for each circuit data; and
a control unit configured to selectively assign the plurality of circuit data to the plurality of programmable logic circuits
so that a total power of all programmable logic circuits minimizes on a condition that the performance requirement of the
circuit data assigned to each programmable logic circuit is within the processing performance of each programmable logic circuit.
|