a trace memory for storing a trace status code and an address output from a semiconductor integrated circuit as trace information, the semiconductor integrated circuit comprising:

a CPU which operates such that

when executing a call instruction, the CPU asserts a first signal and outputs a branch address and a return address relating to the call instruction,

when executing an interrupt branch, the CPU asserts a second signal and outputs a branch address and a return address relating to the interrupt branch, and

when executing a return instruction, the CPU asserts a third signal and outputs a branch address relating to the return instruction;

a stack memory to which the return address output from the CPU is pushed when any one of the first and second signals is asserted and from which the pushed return address is popped when the third signal is asserted;

a comparator for comparing the return address popped from the stack memory and the branch address output from the CPU;

a trace packet control section for receiving a plurality of signals from the CPU to output a trace status code based on the plurality of signals, the plurality of signals including the first through third signals; and

an address register for receiving the branch address output from the CPU and outputting the branch address under control of the trace packet control section,

wherein when the third signal is asserted and the trace packet control section receives from the comparator a comparison result which indicates no match, the trace packet control section orders the address register to output the branch address; and

an execution history tracing section for tracing an execution history of a source program executed by the CPU of the semiconductor integrated circuit by sequentially collating the source program and the trace information stored in the trace memory,

wherein the execution history tracing section operates such that

in any one of a case where a call instruction is detected in the source program and a case where a code which indicates execution of an interrupt branch is detected in the trace information, the execution history tracing section acquires a return address from the source program to push the acquired return address and acquires a branch address from the trace information to trace the acquired branch address, and

when a return instruction is detected in the source program, the execution history tracing section pops the pushed return address to trace the popped return address.