| US 7,533,241 B2 | ||
| Variable size cache memory support within an integrated circuit | ||
| Florent Begon, Antibes (France); Vladimir Vasekin, Cambridge (United Kingdom); Andrew Christophe Rose, Cambridge (United Kingdom); and Nicolas Chaussade, Mouans-Sartoux (France) | ||
| Assigned to ARM Limited, Cambridge (United Kingdom) | ||
| Filed on Dec. 06, 2006, as Appl. No. 11/634,253. | ||
| Claims priority of application No. 0526203.5 (GB), filed on Dec. 22, 2005. | ||
| Prior Publication US 2007/0150640 A1, Jun. 28, 2007 | ||
| Int. Cl. G06F 12/08 (2006.01); G06F 12/10 (2006.01) | ||
| U.S. Cl. 711—212 [711/207] | 16 Claims |
| 1. An integrated circuit comprising:
cache memory means; and
cache controller means coupled to said cache memory means via a cache memory interface having a cache controller side and
a cache memory side, said cache controller means and said cache memory interface supporting operation with cache memory means
of different cache memory sizes connected to said cache memory side of cache memory interface; wherein
said cache memory means includes masking logic means responsive to one or more cache memory size signals received via said
cache memory interface to apply variable masking to an address value generated by said cache controller means to form at least
one masked address value for use in accessing said cache memory means, said masking applied by said masking logic means being
varied in dependence upon said one or more cache memory size signals to match a cache memory size of said cache memory means.
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