| US 7,533,003 B2 | ||
| Weighted event counting system and method for processor performance measurements | ||
| Michael S. Floyd, Austin, Tex. (US); Soraya Ghiasi, Austin, Tex. (US); Thomas W. Keller, Jr., Austin, Tex. (US); Karthick Rajamani, Austin, Tex. (US); Freeman Leigh Rawson, III, Austin, Tex. (US); and Juan C. Rubio, Austin, Tex. (US) | ||
| Assigned to International Business Machines Corporation, Armonk, N.Y. (US) | ||
| Filed on Dec. 05, 2007, as Appl. No. 11/951,310. | ||
| Application 11/951310 is a continuation of application No. 11/565106, filed on Nov. 30, 2006, granted, now 7,340,378. | ||
| Prior Publication US 2008/0133180 A1, Jun. 05, 2008 | ||
| Int. Cl. G01F 19/00 (2006.01) | ||
| U.S. Cl. 702—186 [709/238] | 13 Claims |
| 1. A processor, comprising:
a plurality of functional units each having at least one output event signal of a plurality of event signals for indicating
an occurrence of a plurality of differing events within said processor; and
a weighted performance counter having inputs for receiving said plurality of event signals and updating a performance count
according to states of said plurality of event signals, wherein a change in said performance count according to at least two
of said plurality of events is differently weighted, and whereby a latency between accumulation of performance metrics corresponding
to said events is reduced and said events are further separately weighted according to their correlation to performance of
said processor.
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