| US 7,532,996 B2 | ||
| Semiconductor integrated circuit | ||
| Hiroyuki Kobayashi, Kawasaki (Japan); and Atsumasa Sako, Kawasaki (Japan) | ||
| Assigned to Fujitsu Microelectronics Limited, Tokyo (Japan) | ||
| Filed on Oct. 30, 2006, as Appl. No. 11/589,068. | ||
| Application 11/589068 is a division of application No. 10/980293, filed on Nov. 04, 2004, granted, now 7,149,644. | ||
| Claims priority of application No. 2003-375276 (JP), filed on Nov. 05, 2003; and application No. 2004-187938 (JP), filed on Jun. 25, 2004. | ||
| Prior Publication US 2007/0043522 A1, Feb. 22, 2007 | ||
| Int. Cl. G01K 1/00 (2006.01) | ||
| U.S. Cl. 702—130 | 9 Claims |
| 1. A semiconductor integrated circuit chip comprising:
a memory core to include a plurality of dynamic memory cells arranged in matrix;
a reference voltage generator configured to generate a first boundary voltage corresponding to a first temperature and a second
boundary voltage, which is different from the first boundary voltage, corresponding to a second temperature which is different
from the first temperature;
a temperature detector configured to generate a detection voltage corresponding to a chip temperature, the temperature detector
being coupled to receive the first and second boundary voltages from the reference voltage generator and to compare the first
and second boundary voltages with the detection voltage; and
a refresh control circuit configured to set a refresh cycle of a refresh operation,
wherein, when the chip temperature shifts from below the second temperature to above the first temperature, the refresh control
circuit maintains the refresh cycle when the chip temperature exceeds the second temperature and sets the refresh cycle short
when the chip temperature exceeds the first temperature, and
wherein, when the chip temperature shifts from above the first temperature to below the second temperature, the refresh control
circuit maintains the refresh cycle when the chip temperature falls from the first temperature and sets the refresh cycle
short when the chip temperature falls from the second temperature.
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