| US 7,532,995 B1 | ||
| Interpolator testing circuit | ||
| William Lo, Cupertino, Calif. (US); and Francis Campana, Milpitas, Calif. (US) | ||
| Assigned to Marvell International Ltd., Hamilton (Bermuda) | ||
| Filed on May 08, 2007, as Appl. No. 11/800,816. | ||
| Application 11/800816 is a continuation of application No. 10/852540, filed on May 24, 2004, granted, now 7,246,018. | ||
| Claims priority of provisional application 60/531902, filed on Dec. 22, 2003. | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. G01R 31/28 (2006.01); G06F 11/22 (2006.01) | ||
| U.S. Cl. 702—125 [702/78; 702/79; 375/376; 375/226] | 34 Claims |
| 8. An interpolator testing system comprising:
an interpolator that generates M clock signals having phase shifts in increments of 360/M degrees relative to a reference
clock signal and that outputs one of said M clock signals as a recovered clock signal;
a recovered clock counter that counts an attribute of said recovered clock signal; and
a test module that sequentially selects said M clock signals N times, wherein M and N are integers greater than one.
|