| US 7,532,700 B2 | ||
| Space and power efficient hybrid counters array | ||
| Alan G. Gara, Mount Kisco, N.Y. (US); and Valentina Salapura, Chappaqua, N.Y. (US) | ||
| Assigned to International Business Machines Corporation, Armonk, N.Y. (US) | ||
| Filed on Aug. 21, 2006, as Appl. No. 11/507,310. | ||
| Prior Publication US 2008/0043899 A1, Feb. 21, 2008 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. G06M 3/00 (2006.01) | ||
| U.S. Cl. 377—26 [377/37] | 8 Claims |
| 1. A method for counting events in a computer system comprising:
providing a first counter portion comprising N counter devices, each counter device for receiving signals representing occurrences
of events from N sources and providing a first count value corresponding to a lower order bits of said hybrid counter array;
providing a second counter portion comprising a memory device having N addressable memory locations in correspondence with
said N counter devices, each said addressable memory location being for storing a second count value representing higher order
bits of said hybrid counter array;
monitoring, by a control device, each of said N counter devices of said first counter portion and initiating updating a value
of a corresponding said second count value stored at said corresponding addressable memory location in said second counter
portion,
wherein a combination of said first and second count values provide instantaneous measure of number of events received.
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