| US 7,532,190 B2 | ||
| Multi-resolution driver device | ||
| Hsiao-Yi Lin, Hsinchu (Taiwan); Wei Wang, Hualien (Taiwan); Chaung-Ming Chiu, Jungli (Taiwan); and Yu-Yun Hsu, Hsinchu (Taiwan) | ||
| Assigned to TPO Displays Corp., Chu-Nan (Taiwan) | ||
| Filed on Aug. 10, 2004, as Appl. No. 10/916,361. | ||
| Claims priority of application No. 92122064 A (TW), filed on Aug. 12, 2003. | ||
| Prior Publication US 2005/0068287 A1, Mar. 31, 2005 | ||
| Int. Cl. G09G 3/36 (2006.01) | ||
| U.S. Cl. 345—100 [345/98] | 14 Claims |
| 1. A driver device for a display device, for switching an original resolution to a target resolution in response to a gate
control signal, comprising:
a pixel circuit, generating an image in response to a gate driving signal and a source driving signal;
a gate driving circuit, coupled to said pixel circuit via a plurality of gate lines, one of an original gate driving signal
and a target gate driving signal is selected to be a. gate driving signal in response to a gate control signal, wherein said
original gate driving signal and said target gate driving signal are controlled by a switch circuit; and
a source driving circuit coupled to said pixel circuit via a plurality of source lines, generating said source driving signal
in response to a source control signal,
wherein said gate driving circuit comprises:
a plurality of shift registers, for outputting said gate driving signal; and
a plurality of shift register switches, for switching between following two conditions A and B in order to choose from one
of said original gate driving signal and said target gate driving signal according to said gate control signal, wherein
A: said shift registers activating said shift registers being one stage behind, and
B: said shift registers activating said shift registers being two stages behind,
wherein when said shift register switches switch to condition B, said gate control signal is input to a first shift register
and a second shift register of said shift registers at a same time with respect to the gate control signal, and when said
shift register switches switch to condition A, said gate control signal is input to the first shift register and the second
shift register in series with respect to the gate control signal, and wherein number of distinguishable pixels in response
to the condition B is one half of number of distinguishable pixels in response to the condition A, wherein in condition A,
the first shift register is switched by at least one of the plurality of the register switches to connect to the second shift
register, and the gate control signal is input to the first shift register and the first shift register outputs to the second
shift register, and wherein in condition B, the first shift register is switched by said at least one of the plurality of
register switches to disconnect from the second shift register.
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