| US 7,532,188 B2 | ||
| Clocked inverter circuit, latch circuit, shift register circuit, drive circuit for display apparatus, and display apparatus | ||
| Junichi Yamashita, Tokyo (Japan); and Katsuhide Uchino, Kanagawa (Japan) | ||
| Assigned to Sony Corporation, (Japan) | ||
| Appl. No. 10/581,076 PCT Filed Nov. 18, 2004, PCT No. PCT/JP2004/017529 § 371(c)(1), (2), (4) Date May 31, 2006, PCT Pub. No. WO2005/055427, PCT Pub. Date Jun. 16, 2005. |
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| Claims priority of application No. P2003-401274 (JP), filed on Dec. 01, 2003. | ||
| Prior Publication US 2007/0091014 A1, Apr. 26, 2007 | ||
| Int. Cl. G09G 3/36 (2006.01) | ||
| U.S. Cl. 345—98 | 8 Claims |
| 1. A clocked inverter circuit in which all transistors are same-channel transistors, the clocked inverter circuit comprising:
a first series circuit in which a set of transistors that switch operations in a complimentary manner based on clocks are
connected in series, an input signal being input to one end of the series circuit;
a first inverter circuit including a set of transistors, a connection midpoint of the first series circuit being connected
to a gate of one of the transistors; and
a second inverter circuit including a set of transistors that input an output signal, whose signal level varies in response
to an output of the connection midpoint of the first series circuit, to an opposite end of the first series circuit.
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