| US 7,532,039 B2 | ||
| Clock signal detector | ||
| Hung Yi Kuo, Taipei (Taiwan); Janqlih Hsieh, Taipei (Taiwan); Jenny Chen, Taipei (Taiwan); and Hueilin Chou, Taipei (Taiwan) | ||
| Assigned to Via Technologies, Inc., Taipei (Taiwan) | ||
| Filed on Jan. 03, 2007, as Appl. No. 11/648,593. | ||
| Claims priority of application No. 95100351 A (TW), filed on Jan. 04, 2006. | ||
| Prior Publication US 2007/0152716 A1, Jul. 05, 2007 | ||
| Int. Cl. H03D 13/00 (2006.01) | ||
| U.S. Cl. 327—12 [327/3] | 18 Claims |
| 1. A clock signal detector, comprising:
a first flip-flop, comprising an input end, and coupled to a first clock generator;
a second flip-flop, comprising an input end, coupled to a first signal delayer, and further coupled to said first clock generator
through said first signal delayer;
a third flip-flop, comprising an input end, coupled to a second signal delayer, and further coupled to said first clock generator
through said second signal delayer;
a fourth flip-flop, comprising a clock input end, coupled to a third delayer, and further coupled to a second clock generator
through said third signal delayer; and
a fifth flip-flop, comprising a clock input end, coupled to a fourth signal delayer, and further coupled to said second clock
generator through said fourth signal delayer;
wherein, said clock input ends of said first flip-flop, said second flip-flop and said third flip-flop are respectively coupled
to said second clock generator, said input ends of said fourth flip-flop and fifth flip-flop are respectively coupled to said
first clock generator, and a detecting signal outputted from the output ends of each of said flip-flops.
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