| US 7,531,905 B2 | ||
| Stacked semiconductor device | ||
| Masakzau Ishino, Tokyo (Japan); Hiroaki Ikeda, Tokyo (Japan); and Junji Yamada, Tokyo (Japan) | ||
| Assigned to Elpida Memory, Inc., Tokyo (Japan) | ||
| Filed on Jan. 10, 2007, as Appl. No. 11/651,517. | ||
| Claims priority of application No. 2006-011903 (JP), filed on Jan. 20, 2006. | ||
| Prior Publication US 2007/0181991 A1, Aug. 09, 2007 | ||
| Int. Cl. H01L 23/48 (2006.01); H01L 23/52 (2006.01); H01L 29/40 (2006.01); H01L 23/02 (2006.01) | ||
| U.S. Cl. 257—777 [257/686; 257/778; 257/E21.137; 257/E27.144; 257/E27.161] | 18 Claims |
| 1. A stacked semiconductor device in which a plurality of semiconductor chips including at least first and second semiconductor
chips are stacked, comprising:
an external power supply terminal;
a first connector that electrically connects a power supply wiring arranged in the first semiconductor chip and the external
power supply terminal;
a second connector outside said semiconductor chips that electrically connects a power supply wiring arranged in the second
semiconductor chip and the external power supply terminal; and
a third connector that mutually electrically connects the power supply wirings each provided in adjacent semiconductor chips.
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