| US 7,531,885 B2 | ||
| Photoelectric conversion apparatus and image pick-up system using the photoelectric conversion apparatus | ||
| Akira Okita, Kanagawa (Japan); Katsuhito Sakurai, Tokyo (Japan); Hiroki Hiyama, Kanagawa (Japan); and Hideaki Takada, Kanagawa (Japan) | ||
| Assigned to Canon Kabushiki Kaisha, Tokyo (Japan) | ||
| Filed on Dec. 07, 2006, as Appl. No. 11/608,073. | ||
| Application 11/608073 is a division of application No. 10/971151, filed on Oct. 25, 2004, granted, now 7,187,052. | ||
| Claims priority of application No. 2003-380090 (JP), filed on Nov. 10, 2003. | ||
| Prior Publication US 2007/0085110 A1, Apr. 19, 2007 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. H01L 29/72 (2006.01) | ||
| U.S. Cl. 257—444 [257/431; 257/446; 257/448; 257/450; 257/452; 257/459; 257/461; 257/463] | 2 Claims |

| 1. A photoelectric conversion apparatus comprising a plurality of pixels, each pixel comprising:
a first semiconductor region of a first conductivity type;
a photodiode provided with a second semiconductor region of a second conductivity type disposed in said first semiconductor
region and for converting light into electron charge;
a transfer transistor for transferring the electron charge from said photodiode;
a third semiconductor region of the second conductivity type to which the electron charge from said photodiode is transferred
through said transfer transistor;
an isolation region disposed in the periphery of said photodiode, a gate electrode of said transfer transistor extending to
overlap with the isolation region; and
a fourth semiconductor region of the first conductivity type disposed beneath said isolation region, the impurity concentration
of the fourth semiconductor region being higher than that of the first semiconductor region and the gate electrode of said
transfer transistor extending above at least part of the fourth semiconductor region with said isolation region interposed
therebetween,
wherein the gate electrode is discrete for every pixel, and
the third semiconductor region is formed along of the gate electrode of said transfer transistor, but the width of the third
semiconductor region along the edge of the gate electrode does not extend to an area where part of the gate electrode is laminated
with the isolation region and the fourth semiconductor region.
|