| US 7,531,875 B2 | ||
| Lateral SOI semiconductor device | ||
| Florin Udrea, Cambridge (United Kingdom); and David Garner, Cambridge (United Kingdom) | ||
| Assigned to Cambridge Semiconductor Limited, Cambridge, Cambridgeshire (United Kingdom) | ||
| Appl. No. 10/556,927 PCT Filed May 13, 2003, PCT No. PCT/GB03/02025 § 371(c)(1), (2), (4) Date Jan. 22, 2007, PCT Pub. No. WO2004/102672, PCT Pub. Date Nov. 25, 2004. |
||
| Prior Publication US 2007/0120187 A1, May 31, 2007 | ||
| Int. Cl. H01L 29/94 (2006.01) | ||
| U.S. Cl. 257—343 [257/345] | 25 Claims |
| 1. A lateral semiconductor-on-insulator device comprising:
a semiconductor substrate;
an insulating layer on said semiconductor substrate; and
a lateral semiconductor device on said insulator;
said lateral semiconductor device having:
a first region of a first conductivity type;
a second region of a second conductivity type laterally spaced apart from said first region; and
a drift region extending in a lateral direction between said first region and said second region; and
wherein said drift region comprises at least one first zone and at least one second zone adjacent a said first zone, a said
first zone having said second conductivity type, a said second zone being an insulating zone, a said first zone being tapered
to narrow towards said first region.
|