| US 7,531,861 B2 | ||
| Trench capacitors with insulating layer collars in undercut regions | ||
| Suk-jin Chung, Gyeonggi-do (Korea, Republic of); Seung-hwan Lee, Seoul (Korea, Republic of); Sung-tae Kim, Seoul (Korea, Republic of); Young-sun Kim, Gyeonggi-do (Korea, Republic of); Jae-soon Lim, Seoul (Korea, Republic of); and Young-geun Park, Gyeonggi-do (Korea, Republic of) | ||
| Assigned to Samsung Electronics Co., Ltd, (Korea, Republic of) | ||
| Filed on Feb. 19, 2008, as Appl. No. 12/33,065. | ||
| Application 12/033065 is a division of application No. 11/037626, filed on Jan. 18, 2005, granted, now 7,354,821. | ||
| Claims priority of application No. 10-2004-0020765 (KR), filed on Mar. 26, 2004. | ||
| Prior Publication US 2008/0135876 A1, Jun. 12, 2008 | ||
| Int. Cl. H01L 29/94 (2006.01) | ||
| U.S. Cl. 257—304 [257/190; 257/296; 257/297; 257/298; 257/299; 257/300; 257/301; 257/302; 257/303] | 2 Claims |
| 1. A trench capacitor, comprising:
a silicon substrate;
a first conduction type-doped Si layer on the silicon substrate;
an SiGe layer on the first conduction type-doped Si layer;
a second conduction type-doped Si layer on the SiGe layer opposite to the first conduction type-doped Si layer;
a trench defined in the second conduction type-doped Si layer, the SiGe layer, and the first conduction type-doped Si layer;
an undercut region defined in the SiGe layer and extending laterally along the first and second conduction type-doped Si layers;
an insulating layer collar in the undercut region that extends laterally along the first and second conduction type-doped
Si layers;
a buried plate in the first conduction type-doped Si layer along the trench;
a dielectric layer in the trench on the buried plate; and
a storage electrode on the dielectric layer in the trench opposite to the buried plate.
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