US 7,531,446 B2
Method of manufacturing a semiconductor device
Yong-Woo Lee, Anyang-si (Korea, Republic of); and Kuk-Han Yoon, Yongin-si (Korea, Republic of)
Assigned to Samsung Electronics Co., Ltd, Gyeonggi-do (Korea, Republic of)
Filed on May 05, 2006, as Appl. No. 11/418,067.
Claims priority of application No. 10-2005-0038713 (KR), filed on May 10, 2005.
Prior Publication US 2006/0258145 A1, Nov. 16, 2006
Int. Cl. H01L 21/4763 (2006.01)
U.S. Cl. 438—622  [438/638; 438/668] 21 Claims
OG exemplary drawing
 
1. A method comprising:
providing a first insulation layer pattern on a substrate, the first insulation layer pattern including a first contact hole through which a first region of the substrate is exposed, the first contact hole having increased width versus height from the substrate;
providing a spacer on a sidewall of the first insulation layer pattern;
providing a conductive layer pattern in the first contact hole such that a top surface of the conductive layer pattern is lower than a top surface of the first insulation layer pattern;
providing a second insulation layer pattern on the conductive layer pattern in the first contact hole;
providing a second contact hole on the substrate by etching the first insulation layer pattern using the second insulation layer pattern and the spacer as a self-aligning mask, so that a portion of the first insulation layer pattern remains on a sidewall of the spacer, the second contact hole exposing a second region of the substrate; and
providing a wiring in the second contact hole by filling the second contact hole with a conductive material, the wiring being electrically connected to the substrate.