| US 7,531,429 B2 | ||
| Methods and apparatuses for manufacturing ultra thin device layers for integrated circuit devices | ||
| Peter Tolchinsky, Beaverton, Oreg. (US); Irwin Yablok, Portland, Oreg. (US); Chuan Hu, Chandler, Ariz. (US); and Richard D. Emery, Chandler, Ariz. (US) | ||
| Assigned to Intel Corporation, Santa Clara, Calif. (US) | ||
| Filed on Apr. 03, 2006, as Appl. No. 11/397,412. | ||
| Application 11/397412 is a division of application No. 10/661738, filed on Sep. 11, 2003, granted, now 7,091,108. | ||
| Prior Publication US 2006/0177994 A1, Aug. 10, 2006 | ||
| Int. Cl. H01L 21/46 (2006.01); H01L 21/30 (2006.01); H01L 21/76 (2006.01); H01L 21/00 (2006.01); H01L 21/762 (2006.01) | ||
| U.S. Cl. 438—458 [438/455; 438/960; 438/406; 257/E21.569] | 13 Claims |
| 1. A method of forming a silicon-on-insulator-on-porous-silicon (Si/I/pSi) wafer comprising:
forming a porous silicon layer on a silicon substrate;
depositing a polysilicon layer on the porous silicon layer;
implanting a H2 layer within a donor wafer such that the donor wafer has a surface silicon layer;
depositing an insulator layer on the surface silicon layer of the donor wafer;
bonding the insulator layer to the polysilicon layer to create a bonded pair; and
splitting the bonded pair through the H2 implanted layer in donor wafer leaving a portion of the silicon layer disposed upon
the insulator layer to form a silicon layer of the Si/I/pSi wafer.
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