| US 7,531,402 B2 | ||
| Method of manufacturing semiconductor device with offset sidewall structure | ||
| Kazunobu Ota, Tokyo (Japan); Hirokazu Sayama, Tokyo (Japan); and Hidekazu Oda, Tokyo (Japan) | ||
| Assigned to Renesas Technology Corp., Tokyo (Japan) | ||
| Filed on May 01, 2007, as Appl. No. 11/742,990. | ||
| Application 11/742990 is a continuation of application No. 10/212252, filed on Aug. 06, 2002, granted, now 7,220,637. | ||
| Claims priority of application No. 2001-288918 (JP), filed on Sep. 21, 2001. | ||
| Prior Publication US 2007/0207578 A1, Sep. 06, 2007 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. H01L 21/8238 (2006.01) | ||
| U.S. Cl. 438—199 [257/E27.108] | 1 Claim |
| 1. A method of manufacturing a semiconductor device comprising the steps of:
(a) preparing a semiconductor substrate having a major surface including a first NMOS region for forming a first NMOS transistor
and a first PMOS region for forming a first PMOS transistor;
(b) forming a first gate insulating film in said first NMOS region and said first PMOS region and forming a first gate electrode
and a second gate electrode on said first gate insulating film of said first NMOS region and said first PMOS region, respectively,
and said first gate electrode and said second gate electrode each having side surfaces;
(c) after said step (b), forming a silicon oxide film on said side surface of said first gate electrode and said side surface
of said second gate electrode;
(d) after said step (c), implanting an N-type impurity into said first NMOS region;
(e) after said step (d), forming an insulating film on said silicon oxide film formed on said side surface of said second
gate electrode;
(f) after said step (e), implanting P-type impurity into said first PMOS region.
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