| US 7,531,398 B2 | ||
| Methods and devices employing metal layers in gates to introduce channel strain | ||
| Zhibo Zhang, Plano, Tex. (US); Cloves Rinn Cleavelin, Dallas, Tex. (US); Michael Francis Pas, Richardson, Tex. (US); Stephanie Watts Butler, Richardson, Tex. (US); Mike Watson Goodwin, Murphy, Tex. (US); and Satyavolu Srinivas Papa Rao, Garland, Tex. (US) | ||
| Assigned to Texas Instruments Incorporated, Dallas, Tex. (US) | ||
| Filed on Oct. 19, 2006, as Appl. No. 11/583,280. | ||
| Prior Publication US 2008/0096338 A1, Apr. 24, 2008 | ||
| Int. Cl. H01L 21/336 (2006.01); H01L 21/8234 (2006.01) | ||
| U.S. Cl. 438—197 [438/680; 438/679; 438/684; 257/E21.17; 257/E21.051; 257/E21.278; 257/E21.267; 257/E21.435] | 29 Claims |
| 1. A method of fabricating a semiconductor device, the method comprising:
providing a semiconductor substrate;
forming a gate dielectric layer over the semiconductor substrate;
forming a gate metal stress inducing layer over the gate dielectric layer;
forming an electrically conductive gate electrode layer on the gate metal stress inducing layer;
patterning the gate metal stress inducing layer and the gate electrode layer to define a gate structure; and
forming source and drain regions within the semiconductor substrate on opposite sides of the gate structure.
|