| US 7,370,308 B2 | ||
| Integrated circuit analysis method and program product | ||
| Charles Corey Pie, Fort Collins, Colo. (US); and Gregory Louis Ranson, Fort Collins, Colo. (US) | ||
| Assigned to Hewlett-Packard Development Company, L.P., Houston, Tex. (US) | ||
| Filed on Oct. 27, 2005, as Appl. No. 11/261,951. | ||
| Application 11/261951 is a continuation of application No. 10/059486, filed on Jan. 29, 2002, granted, now 6,996,792. | ||
| Prior Publication US 2006/0048086 A1, Mar. 02, 2006 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. G06F 17/50 (2006.01) | ||
| U.S. Cl. 716—12 [716/2; 716/6; 716/7; 716/11] | 4 Claims |
| 1. A method for making an integrated circuit model for an integrated circuit comprising the steps of:
dividing the integrated circuit into a plurality of connected blocks, each block having a plurality of latches, at least one
of said latches on each of said blocks having a global path connected to a latch from a second of said plurality of blocks;
compressing each of said blocks by removing all of said latches from each of said blocks not required for modeling global
transparency;
identifying said latches in each of said blocks that are connected to more than one incoming global path; and
creating a clone latch for each of said incoming global paths greater than one for each of said identified latches, moving
one of said incoming global paths from each of said identified latches to one of said clone latches whereby each of said identified
latches and each of said clone latches are connected to one incoming global path.
|