| US 7,529,144 B2 | ||
| Hierarchical semiconductor memory device capable of carrying out a disturb refresh test on a memory array basis | ||
| Hiroyuki Sadakata, Osaka (Japan) | ||
| Assigned to Panasonic Corporation, Osaka (Japan) | ||
| Filed on Mar. 15, 2007, as Appl. No. 11/724,213. | ||
| Claims priority of application No. 2006-070587 (JP), filed on Mar. 15, 2006. | ||
| Prior Publication US 2007/0217261 A1, Sep. 20, 2007 | ||
| Int. Cl. G11C 29/00 (2006.01) | ||
| U.S. Cl. 365—201 [365/230.03; 365/190; 365/195] | 4 Claims |
| 1. A semiconductor memory device having a plurality of memory cell arrays each of which composes a group of memory cells and
a sense amplifier circuit, wherein
each of the plurality of memory cell arrays includes:
a plurality of sub-memory cell arrays;
sub-bit lines respectively allocated in each of the plurality of sub-memory cell arrays, and connected to the group of memory
cells;
a main bit line allocated in said each of the plurality of memory cell arrays and connected to the sub-bit lines via selection
switches and also connected to the sense amplifier circuit; and
means for activating, in accordance with a test mode signal externally inputted, each of the selection switches allocated
in said each of the plurality of memory cell arrays.
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