| US 7,529,143 B2 | ||
| Semiconductor memory device, memory module having the same, the test method of memory module | ||
| Shinji Sakuragi, Tokyo (Japan) | ||
| Assigned to Elpida Memory, Inc., Tokyo (Japan) | ||
| Filed on May 17, 2007, as Appl. No. 11/804,179. | ||
| Claims priority of application No. 2006-151958 (JP), filed on May 31, 2006. | ||
| Prior Publication US 2007/0280013 A1, Dec. 06, 2007 | ||
| Int. Cl. G11C 7/00 (2006.01) | ||
| U.S. Cl. 365—200 [365/201] | 15 Claims |
| 1. A semiconductor memory device having a redundant circuit, characterized by comprising:
a chip select circuit operable to determine whether to be selected by a test chip select signal and a redundancy enable signal
and output a chip select flag signal in a chip select test mode.
|