a semiconductor substrate including a memory cell region having a first pattern, a peripheral circuit region having a second pattern being wider than the first pattern, and an interface region located between the memory cell region and the peripheral circuit region,

a P-type well diffusion layer provided on a surface of the semiconductor substrate and surrounding the memory cell region,

an N-type well diffusion layer provided on the surface of the semiconductor substrate and surrounding the P-type well diffusion layer,

a first isolation region provided on the surface of the semiconductor substrate in the interface region, the first isolation region located at a first interface portion between the P-type and the N-type well diffusion layers,

a second isolation region provided on the surface of the semiconductor substrate in the interface region, the second isolation region located between the first isolation region and the memory cell region,

a third isolation region provided on the surface of the semiconductor substrate in the interface region, the third isolation region located at a second interface portion between the N-type well diffusion layer and the semiconductor substrate,

a first guard ring provided on the surface of the semiconductor substrate in the interface region, the first guard ring located between the first and the second isolation regions,

a second guard ring provided on the surface of the semiconductor substrate in the interface region, the second guard ring located between the first and the third isolation regions,

a third guard ring provided on the surface of the semiconductor substrate in the interface region, the third guard ring located between the third isolation region and the peripheral circuit region,

the method comprising:

forming an insulating film on the semiconductor substrate in the memory cell, the interface and the peripheral circuit regions;

forming a mask film above the insulating film;

forming a resist film on the mask film;

exposing the resist film by multiple exposures including a first exposure for forming a first latent image corresponding to the first pattern in the resist film and a second exposure for forming a second latent image corresponding to the second pattern in the resist film, a boundary area of the multiple exposures being set on a corresponding portion to one of the first, second and the third isolation regions, or one of the first and the second guard rings;

forming a resist pattern by developing the resist film; and

forming a mask pattern by etching the mask film with the resist pattern;

etching the insulating film and the semiconductor substrate with the mask pattern to form a plurality of trenches; and

forming isolation films in the trenches to form the first, the second and the third isolation regions.