US 7,526,717 B2
Apparatus and method for coding and decoding semi-systematic block low density parity check codes
Gyu-Bum Kyung, Suwon-si (Korea, Republic of); Se-Ho Myung, Pohang-si (Korea, Republic of); Kyeong-Cheol Yang, Pohang-si (Korea, Republic of); Hyun-Gu Yang, Pohang-si (Korea, Republic of); Dong-Seek Park, Yongin-si (Korea, Republic of); Hong-Sil Jeong, Suwon-si (Korea, Republic of); and Jae-Yoel Kim, Gupo-si (Korea, Republic of)
Assigned to Samsung Electronics Co., Ltd., (Korea, Republic of); and Postech Academy Industry Foundation, (Korea, Republic of)
Filed on Jun. 16, 2005, as Appl. No. 11/154,771.
Claims priority of application No. 10-2004-0044733 (KR), filed on Jun. 16, 2004.
Prior Publication US 2005/0283709 A1, Dec. 22, 2005
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 11/00 (2006.01); H03M 13/03 (2006.01)
U.S. Cl. 714—800  [714/790] 53 Claims
OG exemplary drawing
 
1. A method for coding a semi-systematic block low-density parity check (LDPC) code, the method comprising the steps of:
receiving an information word;
coding the information word into a codeword including the information word, a first parity, a second parity, and a third parity, based on one of a first parity check matrix and a second parity check matrix, depending on a size to be applied when generating the information word into the semi-systematic block LDPC code;
puncturing a part having a degree being at least equal to a predetermined degree from the information word; and
generating the semi-systematic block LDPC code including the information word, a part of which being punctured, the first parity, the second parity, and the third parity.