| US 7,526,703 B2 | ||
| Method of test pattern generation in IC design simulation system | ||
| Min-Shu Wang, Taipei (Taiwan); Chun-You Wang, Taipei (Taiwan); and Chun-Chih Yang, Taipei (Taiwan) | ||
| Assigned to Via Technologies, Inc., Taipei (Taiwan) | ||
| Filed on Jul. 11, 2006, as Appl. No. 11/456,590. | ||
| Claims priority of application No. 94135676 A (TW), filed on Oct. 13, 2005. | ||
| Prior Publication US 2007/0101226 A1, May 03, 2007 | ||
| Int. Cl. G01R 31/28 (2006.01) | ||
| U.S. Cl. 714—741 [714/738; 714/739] | 12 Claims |
| 1. A method of test pattern generation for an integrated circuit (IC) design simulation system, comprising:
merging at least two test vectors into a merged vector, wherein each test vector defines a set of test behaviors; and
compiling and linking the merged vector to generate a merged test pattern able to perform each set of test behaviors independently,
wherein each test vector comprises a test configuration;
wherein merging the at least two test vectors into a merged vector comprises:
comparing test configurations for similarity, and extracting configuration constituents comprising all test configurations
into a common configuration;
combining differences between each test vector and the common configuration into a behavior vector; and
combining the common configuration and all behavior vectors into the merged vector using a predetermined format.
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