| US 7,526,698 B2 | ||
| Error detection and correction in semiconductor structures | ||
| Timothy Joseph Dalton, Ridgefield, Conn. (US); Marc Raymond Faucher, South Burlington, Vt. (US); Paul David Kartschoke, Williston, Vt. (US); and Peter Anthony Sandon, Essex Junction, Vt. (US) | ||
| Assigned to International Business Machines Corporation, Armonk, N.Y. (US) | ||
| Filed on Mar. 23, 2006, as Appl. No. 11/277,306. | ||
| Prior Publication US 2007/0241398 A1, Oct. 18, 2007 | ||
| Int. Cl. G01R 31/28 (2006.01); G01R 31/02 (2006.01) | ||
| U.S. Cl. 714—733 [714/724; 324/763] | 12 Claims |
| 1. A semiconductor structure, comprising:
(a) a first semiconductor chip and a second semiconductor chip,
wherein the first semiconductor chip is on top of and bonded to the second semiconductor chip,
wherein the first semiconductor chip comprises a first functional circuit including a first latch,
wherein the second semiconductor chip comprises a second functional circuit including a second latch,
wherein the first and second functional circuits are functionally identical, and
wherein the second semiconductor chip further comprises a first comparing circuit electrically connected to the second latch;
and
(b) a first coupling via electrically connecting the first latch of the first semiconductor chip to the first comparing circuit
of the second semiconductor chip,
wherein the first comparing circuit is configured to:
(i) receive a first content of the first latch indirectly through the first coupling via,
(ii) receive a second content of the second latch directly, and
(iii) compare the first and second contents and assert a first mismatch signal in response to the first and second contents
being different.
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