| US 7,526,694 B1 | ||
| Integrated circuit internal test circuit and method of testing therewith | ||
| Prabha Jairam, Fremont, Calif. (US); and Himanshu J. Verma, Mountain View, Calif. (US) | ||
| Assigned to Xilinx, Inc., San Jose, Calif. (US) | ||
| Filed on Aug. 03, 2006, as Appl. No. 11/498,368. | ||
| Int. Cl. G01R 31/28 (2006.01); G06F 17/50 (2006.01) | ||
| U.S. Cl. 714—725 [716/4] | 6 Claims |
| 1. A method for in-line product testing of an integrated circuit, comprising:
instantiating a circuit design in programmable logic of the integrated circuit;
obtaining first identification information for a first speed limiting path in the circuit design;
decoupling the first speed limiting path from the circuit design;
coupling the first speed limiting path to a test circuit in the integrated circuit;
verifying whether the first speed limiting path operates at a target frequency using the test circuit;
decoupling the first speed limiting path from the test circuit; and
re-coupling the first speed limiting path to the circuit design.
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