| US 7,526,663 B2 | ||
| Method and apparatus for reducing the power consumed by a computer system | ||
| Don J. Nguyen, Portland, Oreg. (US); Pochang Hsu, Fremont, Calif. (US); Robert T. Jackson, San Jose, Calif. (US); and John W. Horigan, Mountain View, Calif. (US) | ||
| Assigned to Intel Corporation, Santa Clara, Calif. (US) | ||
| Filed on Apr. 11, 2006, as Appl. No. 11/402,527. | ||
| Application 11/402527 is a continuation of application No. 10/159536, filed on May 31, 2002, granted, now 7,062,647. | ||
| Prior Publication US 2006/0184812 A1, Aug. 17, 2006 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. G06F 1/26 (2006.01) | ||
| U.S. Cl. 713—323 [713/321; 323/282] | 19 Claims |
| 1. A voltage regulator comprising:
an output port to supply power to a component of a computer system, a target voltage level of the power to increase if a current
level of the power decreases;
an input port to receive a power state signal, the target voltage level to decrease when the component transitions to a sleep
state as indicated by the power state signal; and
a feedback line to couple the output port to the input port, a feedback voltage of the feedback line to be adjusted according
to the power state signal, wherein the input port is coupled to an input of an inverted logic device, the inverted logic device
having an output coupled to the feedback line to reduce the feedback voltage of the feedback line when the inverted logic
device is turned on.
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