| US 7,526,661 B2 | ||
| Performance state-based thread management | ||
| Jun Nakajima, San Ramon, Calif. (US); and Devadatta V. Bodas, Federal Way, Wash. (US) | ||
| Assigned to Intel Corporation, Santa Clarra, Calif. (US) | ||
| Filed on Dec. 02, 2004, as Appl. No. 11/3,561. | ||
| Prior Publication US 2006/0123251 A1, Jun. 08, 2006 | ||
| Int. Cl. G06F 1/26 (2006.01) | ||
| U.S. Cl. 713—320 [713/300] | 20 Claims |
| 1. A method comprising:
selecting a thread for execution;
identifying a target performance state based on the thread;
selecting a processor core from a plurality of processor cores;
initiating a transition of the processor core to the target performance state if the processor core is not in the target performance
state and none of the remaining cores in the plurality of cores shares a performance state-dependent resource and has a second
target performance state that is shallower than the target performance state; and
scheduling the thread for execution by the processor core.
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