US 7,526,630 B2
	Parallel data processing apparatus
Dave Stuttard, Bristol (United Kingdom); Dave Williams, Emerson Green (United Kingdom); Eamon O'Dea, Bristol (United Kingdom); Gordon Faulds, Dursley (United Kingdom); John Rhoades, Durham, N.C. (US); Ken Cameron, Bristol (United Kingdom); Phil Atkin, Slough (United Kingdom); Paul Winser, Bristol (United Kingdom); Russel David, Wootton Bassett (United Kingdom); Ray McConnell, Clifton (United Kingdom); Tim Day, Edinburgh (United Kingdom); and Trey Greer, Chapel Hill, N.C. (US)
Assigned to Clearspeed Technology, PLC, Bristol (United Kingdom)
Filed on Jan. 04, 2007, as Appl. No. 11/620,014.
Application 11/620014 is a continuation in part of application No. 09/972797, filed on Oct. 09, 2001.
Prior Publication US 2007/0245123 A1, Oct. 18, 2007
Int. Cl. G06F 15/80 (2006.01)

U.S. Cl. 712—10  [712/16; 712/22]

2 Claims

1. A controller operable to control an array of processing elements, the controller comprising: a retrieval unit operable to retrieve instruction items for each of a plurality of instructions streams, each instruction stream having a plurality of instructions items; a combining unit operable to combine the plurality of instruction streams into a serial instruction stream; a distribution unit operable to distribute the serial instruction stream to an array of processing elements; a plurality of instruction stream processors, one for each instruction stream, for controlling the respective instruction streams; a synchronization controller for controlling synchronization between instruction streams; a status block for providing status information regarding each of the instruction streams; and a scheduler connected to receive status information, and operable to determine which of the instruction streams is to be active.