| US 7,526,629 B2 | ||
| Vector processing apparatus with overtaking function to change instruction execution order | ||
| Yasumasa Saida, Tokyo (Japan) | ||
| Assigned to NEC Corporation, Tokyo (Japan) | ||
| Filed on Feb. 23, 2005, as Appl. No. 11/62,561. | ||
| Claims priority of application No. 2004-047066 (JP), filed on Feb. 23, 2004. | ||
| Prior Publication US 2005/0188178 A1, Aug. 25, 2005 | ||
| Int. Cl. G06F 15/00 (2006.01) | ||
| U.S. Cl. 712—2 | 17 Claims |
| 1. A vector processing apparatus comprising:
a main memory;
an instruction issuing section configured to sequentially issue instructions, which contain instructions associated with access
to said main memory;
an overtaking control circuit, which performs overtaking control, configured to output said instructions received from said
instruction issuing section to an instruction executing section in an order determined based on whether there are instructions
belonging to a first specific instruction group before a last instruction, whether there are instructions belonging to a second
specific instruction group in said first specific instruction group before said last instruction, whether there are instructions
belonging to a third specific instruction group before said last instruction, whether said last instruction belongs to a fourth
specific instruction group, and whether an address area of said main memory relating to said last instruction and an address
area of said main memory relating to each of said instructions belonging to said second specific instruction group do not
overlap at all,
wherein the instruction executing section is configured to execute said instructions received from said overtaking control
circuit in an order of reception,
wherein the instructions belonging to the second specific instruction group are of a second type, the instructions belonging
to the third specific instruction group are of a third type, and instructions belonging to the fourth specific instruction
group are of a fourth type,
wherein the second type, the third type, and the fourth type are different from each other,
wherein the overtaking control circuit performs the overtaking control when an address region accessed by a vector store instruction
preceding the last instruction does not overlap an address region accessed by the last instruction,
wherein the last instruction is a vector load instruction,
wherein the overtaking control circuit performs the overtaking control by outputting the vector load instruction to the instruction
executing section before outputting the vector store instruction to the instruction executing section when the address region
accessed by the vector store instruction does not overlap the address region accessed by the vector load instruction.
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