| US 7,526,612 B2 | ||
| Multiport cache memory which reduces probability of bank contention and access control system thereof | ||
| Satoshi Nakazato, Tokyo (Japan) | ||
| Assigned to NEC Corporation, Tokyo (Japan) | ||
| Filed on Nov. 09, 2005, as Appl. No. 11/269,716. | ||
| Claims priority of application No. 2004-326740 (JP), filed on Nov. 10, 2004. | ||
| Prior Publication US 2006/0101207 A1, May 11, 2006 | ||
| Int. Cl. G06F 13/00 (2006.01) | ||
| U.S. Cl. 711—131 [365/230.05] | 32 Claims |
| 1. A multiport cache memory comprising:
an address array in which address information of cache block data is stored; and
a data array in which said cache block data is stored,
wherein said stored cache block data is indexed by a plurality of access addresses to simultaneously execute read operations
on target data corresponding to each of said plurality of access addresses,
wherein each of said plurality of access addresses is divided beginning at the Most Significant Bit into a tag part, an index
part and a block part, and
wherein said address array and said data array are each divided into a plurality of banks which can be uniquely identified
by a lower-order bit of said index part of said access address.
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