| US 7,526,032 B2 | ||
| Sync signal insertion that breaks a maximum bit-run and has a particular detection distance between two or more sync patterns | ||
| Toshiyuki Nakagawa, Kanagawa (Japan); Yoshihide Shimpuku, Kanagawa (Japan); and Tatsuya Narahara, Kanagawa (Japan) | ||
| Assigned to Sony Corporation, Tokyo (Japan) | ||
| Filed on Jun. 08, 2007, as Appl. No. 11/811,023. | ||
| Application 11/811023 is a division of application No. 11/248464, filed on Oct. 12, 2005, granted, now 7,266,153. | ||
| Application 11/248464 is a continuation of application No. 11/077878, filed on Mar. 10, 2005, granted, now 6,983,022. | ||
| Application 11/077878 is a continuation of application No. 09/530074, filed on Jun. 26, 2000, granted, now 6,879,637. | ||
| Claims priority of application No. 10-237044 (JP), filed on Aug. 24, 1998; and application No. PCT/JP99/04562 (WO), filed on Aug. 24, 1999. | ||
| Prior Publication US 2007/0242756 A1, Oct. 18, 2007 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. H04B 14/04 (2006.01) | ||
| U.S. Cl. 375—253 [341/143; 341/67; 369/47.48; 369/59.23; 369/25] | 3 Claims |
| 1. A data-modulating apparatus for modulating data having a basic data length of m bits, to a variable-length code having
a basic code length of n bits, said apparatus comprising:
receiving means for receiving a train of codes; and
sync signal adding means for adding a sync signal to said train of codes after a minimum run, said sync signal being formed
of at least first and second patterns, each pattern breaking a maximum run in channel bits of said train of codes, said first
and second patterns each having six channel bits for identifying said sync signal, said first and second patterns being distinguished
from one another, and said first and second patterns being separated from each other by a detection distance of at least two
between said first and second patterns.
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