| US 7,525,977 B1 | ||
| Control mechanism for mapping cells and packets | ||
| Eduard Lecha, Fremont, Calif. (US); Vasan Karighattam, Davis, Calif. (US); Steve J. Clohset, San Francisco, Calif. (US); Soowan Suh, San Ramon, Calif. (US); Jing Ling, Fremont, Calif. (US); Juan-Carlos Calderon, Fremont, Calif. (US); and Jean-Michel Caia, San Francisco, Calif. (US) | ||
| Assigned to Intel Corporation, Santa Clara, Calif. (US) | ||
| Filed on Jun. 29, 2004, as Appl. No. 10/880,745. | ||
| Int. Cl. H04L 12/28 (2006.01) | ||
| U.S. Cl. 370—411 [370/412] | 12 Claims |
| 1. A device for mapping virtual concatenation data into a frame based on a request for virtual concatenation frame mapping
from a virtual concatenation processing device, comprising:
a buffer configured to receive the request from the virtual concatenation processing device in addition to a channel identifier
associated with the request and further configured to transmit a buffer request for additional virtual concatenation data
along with a buffer channel identifier associated with the buffer request; and
a series of stages connected in series between the buffer and the virtual concatenation processing device and configured to
propagate the virtual concatenation data from the buffer back to the virtual concatenation processing device,
wherein propagation of the virtual concatenation data through the series of stages establishes a fixed delay from transmission
of the request until the virtual concatenation data arrives at the virtual concatenation processing device.
|