| US 7,525,871 B2 | ||
| Semiconductor integrated circuit | ||
| Takeshi Nagai, Yokohama (Japan); and Ryo Haga, Yokohama (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on Apr. 23, 2007, as Appl. No. 11/738,858. | ||
| Application 11/738858 is a continuation of application No. 10/726544, filed on Dec. 04, 2003, granted, now 7,266,025. | ||
| Claims priority of application No. 2003-345975 (JP), filed on Oct. 03, 2003. | ||
| Prior Publication US 2007/0195575 A1, Aug. 23, 2007 | ||
| Int. Cl. G11C 19/00 (2006.01) | ||
| U.S. Cl. 365—240 [365/225.7; 365/200; 365/230.05; 365/94; 365/96; 365/221] | 6 Claims |
| 1. A semiconductor integrated circuit, comprising:
a non-volatile memory element; and
memory blocks that are operated independently,
each memory block including
a memory cell array,
a shift register that receives data from the non-volatile memory element,
a latch circuit that latches data from the shift register, and
a control circuit that controls an operation of the memory cell array based on data latched in the latch circuit, wherein
the operation comprises chip setting operations,
the shift registers of the memory blocks are connected in series, and define a transfer path, and
one end of the transfer path is connected to the non-volatile memory element.
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