| US 7,525,588 B2 | ||
| CMOS APS with stacked avalanche multiplication layer and low voltage readout electronics | ||
| Isao Takayanagi, Tokyo (Japan); and Junichi Nakamura, Tokyo (Japan) | ||
| Assigned to Aptina Imaging Corporation, Grand Cayman (Cayman Islands) | ||
| Filed on Apr. 02, 2008, as Appl. No. 12/78,643. | ||
| Application 12/078643 is a continuation of application No. 10/226190, filed on Aug. 23, 2002, granted, now 7,372,495. | ||
| Prior Publication US 2008/0225133 A1, Sep. 18, 2008 | ||
| Int. Cl. H04N 5/225 (2006.01); H04N 5/335 (2006.01); H01L 27/00 (2006.01) | ||
| U.S. Cl. 348—314 [348/217.1; 348/299; 348/301; 348/310; 257/438; 250/208.1] | 6 Claims |
| 1. An image processing apparatus comprising:
an image sensor for detecting an image and outputting image signals corresponding to the detected image; and
an image processor for processing the image signals outputted from the image sensor, wherein the image sensor comprises:
a charge multiplying photoconversion layer; and
a pixel array having a plurality of pixels,
wherein each pixel comprises:
a charge storage element electrically connected to the charge multiplying photoconversion layer at a first node, and
a protection circuit electrically connected to the charge storage element and the charge multiplying photoconversion layer
at the first node and to a reference potential at a second node for limiting a voltage which accumulates at the charge storage
element.
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