| US 7,525,460 B1 | ||
| Timing loop based on analog to digital converter output and method of use | ||
| Jingfeng Liu, Longmont, Colo. (US); Mats Oberg, Cupertino, Calif. (US); Zachary Keirn, Loveland, Colo. (US); and Bin Ni, Sunnyvale, Calif. (US) | ||
| Assigned to Marvell International Ltd., Hamilton (Bermuda) | ||
| Filed on Jul. 10, 2007, as Appl. No. 11/775,757. | ||
| Claims priority of provisional application 60/830628, filed on Jul. 13, 2006. | ||
| Int. Cl. H03M 1/10 (2006.01) | ||
| U.S. Cl. 341—120 [341/155] | 52 Claims |
| 1. A circuit comprising:
an analog to digital converter (ADC) to receive an analog input signal and convert the analog input signal into a digital
output signal;
a timing generation and compensation circuit responsive to the digital output signal to compensate for asymmetrical qualities
of the analog input signal, if present, and generate a timing signal for said ADC; and
a filter responsive to the digital output signal to generate a filtered signal,
wherein said timing generation and compensation circuit comprises a slicer bias loop that compensates for the asymmetrical
qualities present in the digital output signal.
|