| US 7,525,373 B1 | ||
| Compensation of process and voltage variability in multi-threshold dynamic voltage scaling circuits | ||
| Clarence Rosser Ogilvie, Huntington, Vt. (US); David Solomon Wolpert, Rochester, N.Y. (US); and David James Hathaway, Underhill, Vt. (US) | ||
| Assigned to International Business Machines Corporation, Armonk, N.Y. (US) | ||
| Filed on May 19, 2008, as Appl. No. 12/123,314. | ||
| Int. Cl. H01L 25/00 (2006.01) | ||
| U.S. Cl. 327—564 [327/565; 716/6] | 1 Claim |
| 1. A method of minimizing variation in delay between cells in an integrated circuit, comprising:
grouping the cells into at least two groups, wherein cells are placed in different groups if they are at least one of:
i. different VT type or,
ii. in different regions of the integrated circuit;
connecting cells of a first of the at least two groups of cells to a first set of at least one supply voltage;
connecting cells of a second of the at least two groups of cells to a second set of at least one supply voltage; and
determining a relative delay variation between the at least two groups of cells;
controlling the first set of at least one supply voltage and the second set of at least one supply voltage based on the determined
relative delay variation to reduce the relative delay variation between delays of the at least two groups of cells.
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