a first variable delay circuit which delays an input signal to introduce a first delay into a first edge which is one of a rising edge and a falling edge of the input signal, thereby generates a first delay signal;

a second variable delay circuit which delays the input signal to introduce a second delay into a second edge which is the other one of the rising edge and the falling edge of the input signal, thereby generates a second delay signal;

a control circuit which generates a control signal for controlling the first variable delay circuit and the second variable delay circuit such that the first delay and the second delay are identical; and

a generation circuit which combines the first edge of the first delay signal and the second edge of the second delay signal, thereby generates a third delay signal,

wherein the generation circuit generates a rising edge of the third delay signal based on the first edge of the first delay signal and a falling edge of the third delay signal based on the second edge of the second delay signal, and the generation circuit includes a selection circuit for selecting the first edge of the first delay signal or the second edge of the second delay signal, and a latch circuit for latching the input signal by using the selected edge, and for generating the third delay signal.