US 7,525,360 B1
I/O duty cycle and skew control
Xiaobao Wang, Cupertino, Calif. (US); Chiakang Sung, Milpitas, Calif. (US); and Khai Nguyen, San Jose, Calif. (US)
Assigned to Altera Corporation, San Jose, Calif. (US)
Filed on Apr. 13, 2007, as Appl. No. 11/735,401.
Claims priority of provisional application 60/793864, filed on Apr. 21, 2006.
Int. Cl. H03K 3/017 (2006.01)
U.S. Cl. 327—175  [327/172] 20 Claims
OG exemplary drawing
 
1. An integrated circuit comprising a duty cycle control circuit, the duty cycle control circuit comprising:
an input line coupled with a first input of a signal selection circuit;
a delay chain having an input coupled with the input line and having an output coupled with a second input of the signal selection circuit;
a first logic having a first input coupled with the input line and having an output coupled with a third input of the signal selection circuit, wherein the first logic is used in delaying only the rising edges of a signal on the input line; and
a second logic having a first input coupled with the input line and having an output coupled with a fourth input of the signal selection circuit, wherein the second logic is used in delaying only the falling edges of the signal on the input line.