| US 7,525,356 B2 | ||
| Low-power, programmable multi-stage delay cell | ||
| Keven Hui, San Ramon, Calif. (US); Ting Fang, Pleasanton, Calif. (US); and Hui Yin Seto, San Jose, Calif. (US) | ||
| Assigned to LSI Corporation, Milpitas, Calif. (US) | ||
| Filed on Sep. 14, 2006, as Appl. No. 11/531,829. | ||
| Prior Publication US 2008/0068060 A1, Mar. 20, 2008 | ||
| Int. Cl. H03L 7/00 (2006.01) | ||
| U.S. Cl. 327—161 [327/270; 327/276] | 18 Claims |
| 1. A multi-stage delay cell comprising:
a delay cell input coupled to receive an electrical signal;
a first switch, coupled to the delay cell input and a delay cell output, that switches the electrical signal on a first path
having an associated first delay;
a second switch, coupled in parallel to the first switch, that switches the electrical signal on a second path having an associated
second delay and wherein the second path comprises a first delay stage;
a first control line, coupled to the first delay stage, that electrically couples the second path between the delay cell input
and the delay cell output, and electrically decouples the first data path between the delay cell input and the delay cell
output; and
wherein a first voltage state is set on the output of the second switch prior to electrically coupling the second path between
the delay cell input and the delay cell output and a second voltage state is set on an output of a third switch.
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