| US 7,525,355 B2 | ||
| Digital delay locked loop | ||
| Hong-Yi Huang, Taipei (Taiwan); Shiun-Dian Jan, Taipei County (Taiwan); and Yuan-Hua Chu, Hsinchu County (Taiwan) | ||
| Assigned to Industrial Technology Research Institute, Hsinchu (Taiwan) | ||
| Filed on May 15, 2007, as Appl. No. 11/748,497. | ||
| Claims priority of application No. 95147032 A (TW), filed on Dec. 15, 2006. | ||
| Prior Publication US 2008/0143403 A1, Jun. 19, 2008 | ||
| Int. Cl. H03L 7/06 (2006.01) | ||
| U.S. Cl. 327—158 [327/149] | 21 Claims |
| 1. A digital delay locked loop, comprising:
a plurality of controllable delay circuits, connected in series, each of the controllable delay circuits transmitting a specific
period signal according to delay time determined by a delay control code;
a phase detecting unit, coupled to each of the controllable delay circuits, for sampling the specific period signal at the
transition points of the specific period signal transmitted by each of the controllable delay circuits to generate a sample
output code, and determining the sample output code to provide a counting information, wherein when the sample output code
is a specific sample code, the digital delay locked loop remains in the locked state; and
a delay control unit, coupled to the phase detecting unit, for enabling the delay control code to increase or reduce according
to the counting information.
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