a logic circuit including at least one first pull-up transistor and at least one pull-down transistor which are serially connected between a first node and a first power voltage and receive at least one input signal to generate an output signal, respectively;

a second pull-up transistor connected between a second power voltage and the first node and causing a voltage of the first node to have a voltage level obtained by subtracting a voltage which is less than a threshold voltage thereof from the second power voltage in response to a control voltage; and

a control voltage generator connected between a high voltage which is higher than the second power voltage and a reference voltage which is lower than the high voltage and generating the substantially constant control voltage between the high voltage and the reference voltage, wherein the control voltage generator includes:

first and second resistors and an NMOS transistor having a diode configuration which are serially connected between the high voltage and the reference voltage;

a comparator for comparing a voltage between the first and second resistors to the control voltage to generate a comparison signal; and

a PMOS transistor in which driving ability varies to generate the control voltage in response to the comparison signal,

wherein the NMOS transistor having a diode configuration has a threshold voltage which changes when the threshold voltage of the second pull-up transistor changes and generates the voltage of the second node between the first and second resistors as the control voltage.