| US 7,525,331 B1 | ||
| On-chip critical path test circuit and method | ||
| Prabha Jairam, Fremont, Calif. (US); and Himanshu J. Verma, Mountain View, Calif. (US) | ||
| Assigned to XILINX, Inc., San Jose, Calif. (US) | ||
| Filed on Mar. 06, 2008, as Appl. No. 12/43,833. | ||
| Int. Cl. G01R 31/26 (2006.01) | ||
| U.S. Cl. 324—763 [324/765; 714/724] | 20 Claims |
| 1. A test circuit in an integrated circuit for verifying a critical path of a circuit under test, comprising:
a sequence generator generating a data signal for the critical path;
a source sequential circuit for receiving the data signal coupled to an input of the critical path;
a destination sequential circuit for receiving an output of the critical path;
an analyzer circuit for verification of timing of the critical path by measuring timing from the source sequential circuit
to a clock enable pin or a set/reset pin of the destination sequential circuit; and
a controller circuit for strobing a comparison circuit in the analyzer circuit at a predetermined clock time.
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