US 7,525,183 B2
Surface mount multichip devices
Paddy O'Shea, Inchigeelagh (Ireland); Eamonn Medley, Thurles (Ireland); Finbarr O'Donoghue, Aherla (Ireland); and Gary Horsman, Woodstock, Vt. (US)
Assigned to General Semiconductor, Inc., Melville, N.Y. (US)
Filed on Jul. 10, 2007, as Appl. No. 11/825,991.
Application 11/183504 is a division of application No. 10/617343, filed on Jul. 10, 2003, granted, now 6,919,625.
Application 11/825991 is a continuation of application No. 11/183504, filed on Jul. 18, 2005, granted, now 7,242,078.
Prior Publication US 2008/0017959 A1, Jan. 24, 2008
Int. Cl. H01L 23/495 (2006.01)
U.S. Cl. 257—676  [257/E23.031; 257/E23.034; 257/E23.044; 257/E23.047; 257/E23.052; 257/666; 257/677; 257/685; 257/723; 257/686; 257/675; 257/916; 257/690; 257/691; 257/660; 361/119; 361/820; 361/56; 361/704] 2 Claims
OG exemplary drawing
 
1. A surface-mountable device comprising:
(a) a first chip comprising lower and upper electrical contacts;
(b) a second chip comprising lower and upper electrical contacts;
(c) an undivided first lead frame portion comprising a header region and a lead region, wherein the lower contact of the first chip is in electrical and mechanical connection with the header region of the first lead frame portion;
(d) an undivided second lead frame portion comprising a header region and a lead region, wherein the lower contact of the second chip is in electrical and mechanical connection the header region of the second lead frame portion; and
(e) packaging material encapsulating at least a portion of (i) each of the first and second chips, (ii) the header regions of the first and second lead frame portions, and (iii) the conductive member,
wherein the lead regions of the first and second lead frame portions extend from said packaging material and are adapted to allow the device to be surface-mounted with another electrical component, and wherein the first and second chips are not stacked upon each other within the packaged device, and
further comprising a third chip that comprises lower and upper electrical contacts, wherein the lower contact of the third chip is in electrical and mechanical connection with the header region of the second lead frame portion, and wherein the upper contact of the third chip is in electrical and mechanical connection with said conductive member or a separate conductive member,
wherein a plurality of conductive members are disposed between and in electrical and mechanical connection with the upper electrical contact of the first chip, the upper electrical contact of the second chip, and the upper electrical contact of the third chip, such that the upper electrical contacts of the first, second and third chips are shorted together.