| US 7,525,180 B2 | ||
| Semiconductor mount substrate, semiconductor device and method of manufacturing semiconductor package | ||
| Takeo Ochi, Shiga (Japan) | ||
| Assigned to Panasonic Corporation, Osaka (Japan) | ||
| Filed on Oct. 20, 2006, as Appl. No. 11/583,900. | ||
| Claims priority of application No. 2005-307914 (JP), filed on Oct. 24, 2005; application No. 2006-228510 (JP), filed on Aug. 25, 2006; and application No. 2006-228511 (JP), filed on Aug. 25, 2006. | ||
| Prior Publication US 2007/0090565 A1, Apr. 26, 2007 | ||
| Int. Cl. H01L 23/495 (2006.01) | ||
| U.S. Cl. 257—667 [264/272.11; 264/272.17; 425/572; 425/588; 257/670] | 27 Claims |
| 1. A semiconductor mount substrate provided as a wiring substrate having a plurality of segments arranged at equal intervals
in straight rows to form segment groups, a pair of the segment groups being arranged in parallel with each other, and an outer
connecting portion placed along substrate peripheral edges to surround the segment group in the front row and the segment
group in the rear row, a semiconductor mount area, internal terminals and external terminals being provided on each segment,
the semiconductor mount substrate comprising:
a staggered array of the segments formed by half-pitch shifting the arrangement intervals of the segment group in the front
row and the arrangement intervals of the segment group in the rear row from each other;
rear-row tie bars provided between the segments in the front row to connect the segments in the rear row and the outer connecting
portion; and
front-row tie bars provided between the segments in the rear row to connect the segments in the front row and the outer connecting
portion.
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