| US 7,525,162 B2 | ||
| Orientation-optimized PFETS in CMOS devices employing dual stress liners | ||
| Haizhou Yin, Poughkeepsie, N.Y. (US); Katherine L. Saenger, Ossining, N.Y. (US); Chun-Yung Sung, Poughkeepsie, N.Y. (US); and Kai Xiu, Pleasantville, N.Y. (US) | ||
| Assigned to International Business Machines Corporation, Armonk, N.Y. (US) | ||
| Filed on Sep. 06, 2007, as Appl. No. 11/850,933. | ||
| Prior Publication US 2009/0065867 A1, Mar. 12, 2009 | ||
| Int. Cl. H01L 21/00 (2006.01) | ||
| U.S. Cl. 257—369 [257/255; 257/288; 257/347; 257/351; 257/E21.633; 257/E21.415] | 21 Claims |
| 1. A semiconductor structure comprising:
a substrate containing a first silicon layer having a (110) surface orientation;
a p-type field effect transistor (PFET) located on said first silicon layer and containing a PFET channel between a PFET source
region and a PFET drain region, wherein an azimuthal angle between a direction of current flow in said PFET channel and an
in-plane [1 1 0] crystallographic direction in said first silicon layer is from about 25° to about 55°;
a PFET gate line located over said PFET channel;
a compressive stress liner located on said PFET gate line, a PFET source region, and a PFET drain region, wherein said compressive
stress liner produces a compressive longitudinal strain in said PFET channel;
a second silicon layer having a (001) surface orientation;
an n-type field effect transistor (NFET) located on said second silicon layer and containing an NFET channel, an NFET source
region, and an NFET drain region;
an NFET gate line located over said NFET channel; and
a tensile stress liner located on said NFET gate line, said NFET source region, and said NFET drain region, wherein said tensile
stress liner produces a tensile longitudinal strain in said NFET channel and a secondary tensile transverse stress in said
PFET channel.
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