| US 7,525,158 B2 | ||
| Semiconductor device having pixel electrode and peripheral circuit | ||
| Toshimitsu Konuma, Atsugi (Japan); Akira Sugawara, Atsugi (Japan); Yukiko Uehara, Atsugi (Japan); Hongyong Zhang, Yamato (Japan); Atsunori Suzuki, Kawasaki (Japan); Hideto Ohnuma, Atsugi (Japan); Naoaki Yamaguchi, Yokohama (Japan); Hideomi Suzawa, Atsugi (Japan); Hideki Uochi, Atsugi (Japan); and Yasuhiko Takemura, Atsugi (Japan) | ||
| Assigned to Semiconductor Energy Laboratory Co., Ltd., Kanagawa-ken (Japan) | ||
| Filed on Jul. 20, 2004, as Appl. No. 10/893,889. | ||
| Application 10/893889 is a division of application No. 08/307167, filed on Sep. 16, 1994, granted, now 6,867,431. | ||
| Claims priority of application No. 5-256563 (JP), filed on Sep. 20, 1993; application No. 5-256565 (JP), filed on Sep. 20, 1993; application No. 5-256567 (JP), filed on Sep. 20, 1993; and application No. 5-284287 (JP), filed on Oct. 19, 1993. | ||
| Prior Publication US 2004/0256621 A1, Dec. 23, 2004 | ||
| This patent is subject to a terminal disclaimer. | ||
| Int. Cl. H01L 29/786 (2006.01) | ||
| U.S. Cl. 257—353 [257/59; 257/72; 257/408; 257/E29.269; 257/E29.278] | 22 Claims |
| 1. A semiconductor device comprising:
a substrate;
at least one pixel electrode formed over the substrate;
at least one first thin film transistor electrically connected to the pixel electrode;
a peripheral circuit for driving the first thin film transistor, said peripheral circuit comprising at least one second thin
film transistor and each of the first and second thin film transistors comprising:
a semiconductor film having source and drain regions, a channel region between the source and drain regions, and a pair of
high resistivity regions between the channel region and the source and drain regions, respectively;
a gate insulating film adjacent to the channel region; and
a gate electrode adjacent to the channel region with the gate insulating film interposed therebetween,
wherein the pair of high resistivity regions is partly overlapped with the gate electrode in the second thin film transistor,
and
wherein any overlap of the pair of high resistivity regions with the gate electrode in the second thin film transistor is
greater than any overlap of the pair of high resistivity regions with the gate electrode in the first thin film transistor.
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