| US 7,525,154 B2 | ||
| Semiconductor substrate, manufacturing method therefor, and semiconductor device | ||
| Hajime Nagano, Yokohama (Japan); Ichiro Mizushima, Yokohama (Japan); and Kiyotaka Miyano, Fujisawa (Japan) | ||
| Assigned to Kabushiki Kaisha Toshiba, Tokyo (Japan) | ||
| Filed on May 25, 2004, as Appl. No. 10/852,511. | ||
| Claims priority of application No. 2004-074969 (JP), filed on Mar. 16, 2004. | ||
| Prior Publication US 2005/0205929 A1, Sep. 22, 2005 | ||
| Int. Cl. H01L 29/72 (2006.01) | ||
| U.S. Cl. 257—347 [257/190; 257/194; 257/401; 257/616; 257/618] | 8 Claims |
| 1. A semiconductor substrate, comprising:
a support substrate including a first region and a second region, the second region being adjacent to the first region;
a first insulating layer formed on the support substrate in the first region, the first insulating layer including a first
side wall facing the second region;
a relaxed silicon germanium (SiGe) layer formed on the first insulating layer, the relaxed SiGe layer including a second side
wall facing the second region;
a second insulating layer formed on the second side wall, the second insulating layer including a third side wall flush with
the second side wall;
a third insulating layer formed on the first and second side walls, the third insulating layer including a fourth side wall
facing the second region and a lower end portion thereof spaced apart from a first upper surface of the support substrate;
a silicon layer formed on the support substrate in the second region, the silicon layer including a fifth side wall contacting
the first and fourth side walls;
a strained silicon layer formed on the relaxed SiGe layer, the strained silicon layer including a second upper surface; and
a relaxed silicon layer formed above the silicon layer, the relaxed silicon layer including a third upper surface flush with
the second upper surface.
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